As dynamic random access memory (DRAM) technologies are scaled to smaller dimensions and used in various operating environments and form factors relatively high levels of power usage by DRAM may require mitigation by careful design to reduce power usage. These relatively high levels become problematic in large computing systems such as data centers were even small amounts of extra power usage quickly raise costs associated with operating large data centers. Also, in small form factors such as smart phones or tablets, performance advances made in low power processors may be reduced if associated DRAM used in these devices fails to have similar advances in reducing power. For example, these small form factor devices may suffer from reduced performance if DRAM capacity is reduced to compensate for excessive power usage by DRAM.